Join OpenAI as a Physical Design Engineer to develop AI-native silicon and system-level solutions. Collaborate with RTL designers and optimize design for performance and cost efficiency.
OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform.
In this role, you will:
- Develop, build and own tools, flows and methodologies for physical implementation
- Own physical implementation of floorplan blocks from floorplanning to final signoff
- Collaborate with RTL designers to drive optimal block implementation solutions
- Analyze and optimize design for timing, power, and area trade-offs, working in collaboration with EDA vendors and ASIC partners
Qualifications:
- BS w/ 4+ or MS with 2+ years or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development
- Demonstrated success in taping out complex silicon designs
- Hands-on experience with block physical implementation and PPA convergence
- Strong coding experience with python, bazel, TCL
- Strong experience building physical design tools, flows and methodologies
- Strong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification and timing closure.
- Deep familiarity with industry-standard tools and flows for physical synthesis, PNR, LEC and power estimation
Bonus:
- Experience with AI or HPC-focused chips
- Experience with optimizing PPA for high performance compute cores
- Hands-on experience with top-level design methodologies